1. Field of the Invention
The present invention relates to a gate drive device for driving MOS transistors, and particularly to a gate drive device for driving electric power MOS transistors (power MOS transistors).
2. Description of the Background Art
Nowadays, inverter circuits are used as AC motor driving circuits. Such inverter circuits use power MOS transistors.
In such an inverter circuit having power MOS transistors, when an MOS transistor connected with an inductive load, e.g. a motor, turns off, then a recovery surge voltage (hereinafter referred to as a surge voltage) appears between its main electrodes (between the collector and emitter). In general, such a surge voltage is likely to become large because of poor recovery characteristics of the parasitic diode in the power MOS transistor. The surge voltage may possibly lead to breakage of the power MOS transistor. Accordingly, power MOS transistor drive circuits capable of reducing the surge voltage have been suggested (for example, refer to Japanese Patent Application Laid-Open No. 2001-24492, pp. 3-5, FIGS. 1-6).
In the drive circuit shown in this reference, a diode is interposed between the source terminal of a power MOS transistor and an off switching circuit connected to its gate terminal. Then, when gate charge is drawn out through the off switching circuit to turn off the power MOS transistor, the gate-source voltage is kept at a predetermined value (the forward voltage of the diode). That is to say, a certain level of charge remains between the gate and source because of the diode forward voltage, and it is then possible to lower the level of the surge voltage that is caused by charging of the capacitance component of the power MOS transistor.
Now, surge voltage may occur also during off periods of power MOS transistors. For example, in an inverter having two series-connected power MOS transistors, when one power MOS transistor turns off and then the other power MOS transistor turns on after that, a recovery phenomenon occurs in the parasitic diode in said one power MOS transistor being off, causing a surge voltage between the collector and emitter of that power MOS transistor.
This surge voltage can be reduced by the drive circuit described in the reference shown above. However, the insertion of a diode between the off switching circuit and the source terminal deteriorates the gate charge extraction characteristic of the power MOS transistor, leading to a large switching loss at turning off.
Concerning a circuit having series-connected MOS transistors, such as an inverter circuit, an object of the present invention is to provide a gate drive device capable of reducing a surge voltage that occurs during off periods, while suppressing an increase in switching loss when the MOS transistors turn off.
According to a first aspect of the invention, a gate drive device drives first and second MOS transistors that are series-connected to each other. In the drive device, when one of the first and second MOS transistors is turned off and then the other is turned on after that with a predetermined timing, the one MOS transistor is temporarily placed in an on state for a predetermined time period that is synchronized with the predetermined timing.
According to a second aspect of the invention, a gate drive device has a drive circuit for driving an MOS transistor. The drive circuit includes first and second terminals that are connectable respectively to a gate and a source of the MOS transistor, first and second voltage sources, first to third switching elements and a resistor, and a control circuit for controlling the first to third switching elements and the second voltage source. The first voltage source supplies a driving voltage for driving the MOS transistor. The second voltage source is connected to the first terminal and supplies a predetermined voltage that is less than a threshold voltage at which the MOS transistor turns on. The first switching element is connected between the first voltage source and the first terminal. The second switching element is connected between the first terminal and the second terminal. The third switching element and the resistor are series-connected to each other and parallel-connected to the second switching element. After turning off the first switching element and turning on the second switching element, and according to a predetermined timing and for a predetermined time period, the control circuit temporarily places the first and second switching elements in an off state and the third switching element in an on state and applies the predetermined voltage from the second voltage source to the first terminal.
According to a third aspect of the invention, a gate drive device has a drive circuit for driving an MOS transistor. The drive circuit includes first and second terminals that are connectable respectively to a gate and a source of the MOS transistor, a voltage source, first to third switching elements, first and second resistors, and a control circuit for controlling the first, second, and third switching elements.
The voltage source supplies a driving voltage for driving the MOS transistor. The first switching element and the first resistor are series-connected to each other and connected between the voltage source and the first terminal. The second switching element is connected between the first terminal and the second terminal. The third switching element and the second resistor are series-connected to each other and parallel-connected to the second switching element. After turning off the first switching element and turning on the second switching element, and according to a predetermined timing and for a predetermined time period, the control circuit temporarily places the first and third switching elements in an on state and places the second switching element in an off state.
When one of the first and second MOS transistors is turned off and then the other is turned on after that with a predetermined timing, the one MOS transistor is temporarily placed in an on state for a predetermined time period that is synchronized with the predetermined timing. This reduces the surge voltage that takes place in the one MOS transistor as the other MOS transistor turns on. Also, since no diode is interposed between the gate and source of the first and second MOS transistors, an increase in switching loss can be prevented when they turn off.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.